Generally, a desired semiconductor device, such as an integrated circuit (IC), is manufactured in such a way that various processing units are arranged in a processing system which constructs a manufacturing line, and various processes, such as a film forming process, an oxidation/diffusion process, an etching process, a modification process and an annealing process, are repeatedly performed on a semiconductor wafer (see, for example, Japanese Patent Laid-open Publication Nos. 10-223732, 2001-338969 and 2005-236094).
Meanwhile, the existence of defects, including the attachment of foreign materials, such as particles, is one of the major causes for the decreased yields of the semiconductor devices. Therefore, it is necessary to detect the excessive defects on a wafer over an allowable level in a short period of time to thereby suppress the decrease in yield to a minimum. Accordingly, the existence and distribution pattern of defects occurring on the surface of a wafer is appropriately measured in the manufacturing line. Further, when an operator who performs the measurement detects the excessive defects on a wafer over an allowable level, the operator should specify the specific portion (the cause portion) of the processing system, which is a cause of the defects, and take measures of how to prevent defects from occurring.
In this case, the operator compares the defect distribution pattern, obtained by the measurement, with the characteristic configuration of the specific portion of the processing system with the naked eyes (visually), and then specifies the cause portion. Specifically, the operator compares the characteristic configuration of each of the various components of the processing system, which is based on a design drawing or the memory of the operator, for example, the arrangement configuration of gas spray holes of a shower head included in each processing chamber, with the defect distribution pattern of the surface of a wafer. Thereafter, the operator specifies the cause portion which has caused the defects by finding a component such as the shower head having the configuration that is most coincident with the defect distribution pattern.
Further, devices for inspecting defects on a semiconductor wafer have made startling progress recently. Therefore, defects, including not only foreign materials such as particles attached on a wafer but also a scratch on the wafer and short circuit or disconnection of a wiring line, can be detected and monitored at a high speed.
However, when specifying a cause portion which has caused the defects, the operator should compare the characteristic configuration of the specific portion of the processing system with the defect distribution pattern of a wafer with the naked eyes. Therefore, the accuracy of the comparative determination is influenced by the knowledge or experience of the operator regarding components. Further, it is difficult to quantitatively obtain the degree of coincidence between the characteristic configuration and the defect distribution pattern.
Further, since the defect distribution pattern should be compared with a plurality of reference patterns with the naked eyes, a long time is required to specify a cause portion which has caused the defects.
Meanwhile, as disclosed in Japanese Patent Laid-open Publication No. 2005-236094, a device which has caused inferiority may be specified by performing probe inspection after completing products such as integrated circuits (ICs), and comparing a probe inspection map with a defect map. This enables to specify the processing unit which has caused inferiority to the products. In this technology, the cause of inferiority is specified through the inspection after products are completed. Therefore, the same cause of inferiority affects a number of wafers which are processed before the inspection is performed, so that a number of defective and wasteful wafers may occur.